The present-day fabrication of semiconductor wafers is a complex multi-step process. In a typical process, various materials are sequentially applied to a substrate in order to build up a substantially laminar structure. After a layer has been laid down, selected regions of that layer are commonly modified or removed. Such manipulations often impart nonplanarity to the top surface of the layer. Nonplanarity, also known as uneven surface topography, is undesirable for a number of reasons, one of which is that laying down a subsequent layer is made more difficult if the underlying layer is nonplanar. Therefore, a common step during semiconductor wafer fabrication is to planarize the surface of the wafer, by a process known as planarization or polishing, where these terms are often used interchangeably.
There are a large number of specific processes that can be used to planarize the surface of a semiconductor wafer, a few of which will be discussed later herein. However, it is generally the case that planarization will selectively remove surface material that constitutes the highest points of the surface, i.e., the points of the surface furthest from the base of the semiconductor wafer. In this way, the high points are removed and the surface topography of the wafer is planarized, also called leveled or flattened. The planarization process can be carried out on an already planar surface, in which case an entire layer of a semiconductor wafer may be removed. Regardless of the amount of material that is removed by a planarization process, a typical consequence of planarization is that a residue is left on the planarized surface. This residue may be termed planarization residue.
The exact identity of the residue depends on the details of the planarization process, however at a minimum the residue typically includes bits and particles which have been dislodged from the surface, and often includes materials that were used to assist the planarization process. At the end of the planarization process, this residue should be completely removed before any further layers may be laid down upon the semiconductor surface.
Pure water, optionally in combination with scrubbing, is commonly used in the art to remove planarization residue. However, the prior art also describes methods and compositions which have been developed to more effectively and efficiently remove planarization residue from a semiconductor surface. For example, U.S. Pat. No. 5,478,436 to Winebarger et al. is directed to applying a cleaning solution to a semiconductor substrate having metal contaminants thereon, in order to remove the metal contaminants. The Winebarger et al. cleaning solution comprises an organic solvent and a compound containing fluorine. As another example, U.S. Pat. No. 5,389,194 to Rostoker et al. is directed to a method of cleaning polishing residue from a semiconductor device. The Rostoker et al. method uses a cleaning solution consisting essentially of phosphoric acid and hydrofluoric acid.
As recognized by both Winebarger et al. and Rostoker et al., a problem with the use of chemical-containing cleaning solutions for removing planarization residue is that, in order for the cleaning process to be effective, the cleaning solutions are so strong that they degrade/dissolve the surface layer itself. That is, the cleaning solutions cause undesirable degradation and/or removal of the surface of the planarized layer. While Winebarger et al. and Rostoker et al. both purport to address this problem, there is still a significant need in the art for satisfactory processes and cleaning solutions for selectively removing planarization residue from a semiconductor surface.